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CY7C419/21/25/29/33256/512/1K/2K/4K x 9 Asynchronous FIFO
CY7C419/21/25/29/33
256/512/1K/2K/4K x 9 Asynchronous FIFO
Features

Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and CY7C432/3 are first-in first-out (FIFO) memories offered in 600-mil wide and 300-mil wide packages. There are 256, 512, 1,024, 2,048, and 4,096 words respectively by 9 bits wide. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in parallel. This eliminates the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. The read and write operations may be asynchronous; each can occur at a rate of 50 MHz. The write operation occurs when the write (W) signal is LOW. Read occurs when read (R) goes LOW. The nine data outputs go to the high impedance state when R is HIGH. A Half Full (HF) output flag that is valid in the standalone and width expansion configurations is provided. In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it is activated. In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFOs to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and guard rings.
Asynchronous first-in first-out (FIFO) buffer memories 256 x 9 (CY7C419) 512 x 9 (CY7C421) 1K x 9 (CY7C425) 2K x 9 (CY7C429) 4K x 9 (CY7C433) Dual-ported RAM cell High speed 50 MHz read and write independent of depth and width Low operating power: ICC = 35 mA Empty and full flags (Half Full flag in standalone) TTL compatible Retransmit in standalone Expandable in width PLCC, 7x7 TQFP, SOJ, 300-mil, and 600-mil DIP Pb-free packages available Pin compatible and functionally equivalent to IDT7200, IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201, AM7202, AM7203, and AM7204
Logic Block Diagram
Cypress Semiconductor Corporation Document #: 38-06001 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised December 09, 2008
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Pin Configurations
Figure 1. 32-Pin PLCC/LCC Figure 3. 32-PIn TQFP
Figure 2. 28-Pin DIP
Table 1. Selection Guide 4K x 9 Frequency (MHz) Maximum Access Time (ns) ICC1 (mA) -10 50 10 35 -15 40 15 35 -20 33.3 20 35 -25 28.5 25 35 -30 25 30 35 -40 20 40 35 -65 12.5 65 35
Document #: 38-06001 Rev. *C
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Maximum Rating
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[1] Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied.. -55C to +125C Supply Voltage to Ground Potential................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ................................................-0.5V to +7.0V DC Input Voltage ............................................-0.5V to +7.0V Power Dissipation.......................................................... 1.0W Electrical Characteristics Over the Operating Range[3] Parameter VOH VOL VIH VIL IIX IOZ IOS Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Output Short Circuit Current[5]
Output Current, into Outputs (LOW)............................ 20 mA Static Discharge Voltage............................................ >2000V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to + 70C -40C to +85C VCC 5V 10% 5V 10%
Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA Commercial Industrial GND < VI < VCC R > VIH, GND < VO < VCC VCC = Max., VOUT = GND
All Speed Grades
Min 2.4 2.0 2.2
[4]
Max 0.4 VCC VCC 0.8 +10 +10 -90
Unit V V V V A A mA
-10 -10
Notes 1. Single Power Supply: The voltage on any input or I/O pin can not exceed the power pin during power-up. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. VIL (Min.) = -2.0V for pulse durations of less than 20 ns. 5. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
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Electrical Characteristics Over the Operating Range
Parameter ICC ICC1 ISB1 ISB2 Description Operating Current Test Conditions VCC = Max., IOUT = 0 mA f = fMAX VCC = Max., IOUT = 0 mA F = 20 MHz All Inputs = VIH Min. Commercial Industrial Commercial
-10 -15 -20 -25
Min
Max 85
Min
Max 65 100 35
Min
Max 55 90 35
Min
Max 50 80 35
Unit mA
Operating Current
35
mA
Standby Current
Power-Down Current All Inputs > VCC -0.2V
Commercial Industrial Commercial Industrial
10 5
10 15 5 8
10 15 5 8
10 15 5 8
mA mA
Electrical Characteristics Over the Operating Range[3]
Parameter ICC ICC1 ISB1 ISB2 Description Operating Current Test Conditions VCC = Max., IOUT = 0 mA f = fMAX VCC = Max., IOUT = 0 mA F = 20 MHz All Inputs = VIH Min. Commercial Industrial Commercial
-30 -40 -65
Min
Max 40 75 35
Min
Max 35 70 35
Min
Max 35 65 35
Unit mA
Operating Current
mA
Standby Current
Power-Down Current All Inputs > VCC -0.2V
Commercial Industrial Commercial Industrial
10 15 5 8
10 15 5 8
10 15 5 8
mA mA
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 4.5V Max 6 6 Unit pF pF
Note 6. Tested initially and after any design or process changes that may affect these parameters.
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Switching Characteristics Over the Operating Range[7, 8]
Parameter tRC tA tRR tPR tLZR[6,9] tDVR[9,10] tHZR[6,9,10] tWC tPW tHWZ[6,9] tWR tSD tHD tMRSC tPMR tRMR tRPW tWPW tRTC tPRT tRTR tEFL tHFH tFFH tREF tRFF tWEF tWFF tWHF tRHF tRAE tRPE tWAF tWPF tXOL tXOH Description Read Cycle Time Access Time Read Recovery Time Read Pulse Width Read LOW to Low Z Data Valid After Read HIGH Read HIGH to High Z Write Cycle Time Write Pulse Width Write HIGH to Low Z Write Recovery Time Data Set-Up Time Data Hold Time MR Cycle Time MR Pulse Width MR Recovery Time Read HIGH to MR HIGH Write HIGH to MR HIGH Retransmit Cycle Time Retransmit Pulse Width Retransmit Recovery Time MR to EF LOW MR to HF HIGH MR to FF HIGH Read LOW to EF LOW Read HIGH to FF HIGH Write HIGH to EF HIGH Write LOW to FF LOW Write LOW to HF LOW Read HIGH to HF HIGH Effective Read from Write HIGH Effective Read Pulse Width After EF HIGH Effective Write from Read HIGH Effective Write Pulse Width After FF HIGH Expansion Out LOW Delay from Clock Expansion Out HIGH Delay from Clock
-10 -15 -20 -25
Min 20 10 10 3 5
Max 10
Min 25 10 15 3 5
Max 15
Min 30 10 20 3 5
Max 20
Min 35 10 25 3 5
Max 25
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15 20 10 5 10 6 0 20 10 10 10 10 20 10 10 20 20 20 10 10 10 10 10 10 10 10 10 10 10 10 15 15 25 15 5 10 8 0 25 15 10 15 15 25 15 10
15 30 20 5 10 12 0 30 20 10 20 20 30 20 10 25 25 25 15 15 15 15 15 15 15 20 15 20 15 15
15 35 25 5 10 15 0 35 25 10 25 25 35 25 10 30 30 30 20 20 20 20 20 20 20 25 20 25 20 20
18
35 35 35 25 25 25 25 25 25 25 25 25 25
Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30 pF load capacitance, as in part (a) of AC Test Load and Waveforms, unless otherwise specified. 8. See the last page of this specification for Group A subgroup testing information. 9. tHZR transition is measured at +200 mV from VOL and -200 mV from VOH. tDVR transition is measured at the 1.5V level. tHWZ and tLZR transition is measured at 100 mV from the steady state. 10. tHZR and tDVR use capacitance loading as in part (b) of AC Test Load and Waveforms.
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Switching Characteristics Over the Operating Range[7, 8] (continued)
Parameter tRC tA tRR tPR tLZR
[6,9]
Description Read Cycle Time Access Time Read Recovery Time Read Pulse Width Read LOW to Low Z Data Valid After Read HIGH Read HIGH to High Z Write Cycle Time Write Pulse Width Write HIGH to Low Z Write Recovery Time Data Set-Up Time Data Hold Time MR Cycle Time MR Pulse Width MR Recovery Time Read HIGH to MR HIGH Write HIGH to MR HIGH Retransmit Cycle Time Retransmit Pulse Width Retransmit Recovery Time MR to EF LOW MR to HF HIGH MR to FF HIGH Read LOW to EF LOW Read HIGH to FF HIGH Write HIGH to EF HIGH Write LOW to FF LOW Write LOW to HF LOW Read HIGH to HF HIGH Effective Read from Write HIGH Effective Read Pulse Width After EF HIGH Effective Write from Read HIGH Effective Write Pulse Width After FF HIGH Expansion Out LOW Delay from Clock Expansion Out HIGH Delay from Clock
-30
-40
-65
Min 40
Max 30
Min 50
Max 40
Min 80
Max 65
Unit ns ns ns ns ns ns
10 30 3 5 20 40 30 5 10 18 0 40 30 10 30 30 40 30 10 40 40 40 30 30 30 30 30 30 30 30 30 30 30 30
10 40 3 5 20 50 40 5 10 20 0 50 40 10 40 40 50 40 10 50 50 50 35 35 35 35 35 35 35 40 35 40 40 40
15 65 3 5 20 80 65 5 15 30 0 80 65 15 65 65 80 65 15 80 80 80 60 60 60 60 60 60 60 65 60 65 65 65
tDVR[9,10] tHZR tWC tPW tHWZ[6,9] tWR tSD tHD tMRSC tPMR tRMR tRPW tWPW tRTC tPRT tRTR tEFL tHFH tFFH tREF tRFF tWEF tWFF tWHF tRHF tRAE tRPE tWAF tWPF tXOL tXOH
[6,9,10]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Switching Waveforms
Figure 4. Asynchronous Read and Write
tA tRC tRR tPR tA
R tLZR Q0-Q 8
tDVR DATA VALID
tHZR DATA VALID
tPW W
tWC
tWR
tSD D0-D 8
tHD DATA VALID
DATA VALID
Figure 5. Master Reset
tMRSC [12] MR R, W [11] tPMR
tRPW tWPW tEFL tRMR
EF tHFH HF tFFH FF
Figure 6. Half-full Flag
HALF FULL W tRHF R tWHF HF HALF FULL+1 HALF FULL
Notes 11. W and R VIH around the rising edge of MR 12. tMRSC = tPMR + tRMR.
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Switching Waveforms (continued)
Figure 7. Last Write to First Read Full Flag
LAST WRITE FIRST READ ADDITIONAL READS FIRST WRITE
R
W tWFF FF tRFF
Figure 8. Last Read to First Write Empty Flag
W LAST READ FIRST WRITE ADDITIONAL WRITES FIRST READ
R tREF EF tA DATA OUT VALID VALID tWEF
Figure 9. Retransmit[13]
tRTC[14] FL/RT tPRT
R,W tRTR
Notes 13. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTC. 14. tRTC = tPRT + tRTR.
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Switching Waveforms (continued)
Figure 10. Empty Flag and Read Data Flow-through Mode
DATA IN W tRAE R tREF EF tRPE
tWEF tHWZ
tA DATA VALID
DATA OUT
Figure 11. Full Flag and Write Data Flow-through Mode
R tWAF W tRFF FF DATA IN tA DATA OUT DATA VALID DATA VALID tSD tWFF tWPF
tHD
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Switching Waveforms (continued)
Figure 12. Expansion Timing Diagrams
WRITE TO LAST PHYSICAL LOCATION OF DEVICE 1 W tWR XO1(XI2)[15] tXOL tXOH WRITE TO FIRST PHYSICAL LOCATION OF DEVICE 2
tSD D0-D 8
tHD
tSD
tHD
DATA VALID
DATA VALID
READ FROM LAST PHYSICAL LOCATION OF DEVICE 1 R tRR
[15]
READ FROM FIRST PHYSICAL LOCATION OF DEVICE 2
tXOL
tXOH tHZR
XO1(XI2)
tLZR Q0-Q 8 tA
tDVR DATA VALID tA
tDVR DATA VALID
Note 15. Expansion Out of device 1 (XO1) is connected to Expansion In of device 2 (XI2)
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Architecture
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, CY7C432/3 FIFOs consist of an array of 256, 512, 1024, 2048, 4096 words of 9 bits each (implemented by an array of dual-port RAM cells), a read pointer, a write pointer, control signals (W, R, XI, XO, FL, RT, MR), and Full, Half Full, and Empty flags.
The retransmit feature is beneficial when transferring packets of data. It enables the receiver to acknowledge receipt of data and retransmit, if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. R and W must both be HIGH while and tRTR after retransmit is LOW. With every read cycle after retransmit, previously accessed data and not previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are also transmitted. FIFO, up to the full depth, can be repeatedly retransmitted.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is necessary to achieve truly asynchronous operation of the inputs and outputs. A second benefit is that the time required to increment the read and write pointers is much less than the time required for data propagation through the memory, which is the case if memory is implemented using the conventional register array architecture.
Resetting the FIFO
Upon power up, the FIFO must be reset with a Master Reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (HF) and Full flags (FF) being HIGH. Read (R) and write (W) must be HIGH tRPW/tWPW before and tRMR after the rising edge of MR for a valid reset cycle. If reading from the FIFO after a reset cycle is attempted, the outputs are in the high impedance state.
Standalone/Width Expansion Modes
Standalone and width expansion modes are set by grounding Expansion In (XI) and tying First Load (FL) to VCC. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data appearing at the inputs (D0-D8) tSD before and tHD after the rising edge of W will be stored sequentially in the FIFO. The EF LOW-to-HIGH transition occurs tWEF after the first LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW tWHF after the falling edge of W following the FIFO actually being Half Full. Therefore, the HF is active once the FIFO is filled to half its capacity plus one word. HF will remain LOW while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs tRHF after the rising edge of R when the FIFO goes from half full +1 to half full. HF is available in standalone and width expansion modes. FF goes LOW tWFF after the falling edge of W, during the cycle in which the last available location is filled. Internal logic prevents overrunning a full FIFO. Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tRFF after a read from a full FIFO.
when, during a MR cycle, Expansion Out (XO) of one device is connected to Expansion In (XI) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode the First Load (FL) input, when grounded, indicates that this part is the first to be loaded. All other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and pulsed LOW again when the last physical location is read. Only one FIFO is enabled for read and one for write at any given time. All other devices are in standby. FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created of word widths in increments of 9. When expanding in depth, a composite FF must be created by ORing the FFs together. Likewise, a composite EF is created by ORing the EFs together. HF and RT functions are not available in depth expansion mode.
Depth Expansion Mode Depth expansion mode (see Figure 13 on page 12) is entered
Use of the Empty and Full Flags
To achieve maximum frequency, the flags must be valid at the beginning of the next cycle. However, because they can be updated by either edge of the read or write signal, they must be valid by one-half of a cycle. Cypress FIFOs meet this requirement; some competitors' FIFOs do not. The reason for why the flags should be valid by the next cycle is complex. The "effective pulse width violation" phenomenon can occur at the full and empty boundary conditions, if the flags are not properly used. The empty flag must be used to prevent reading from an empty FIFO and the full flag must be used to prevent writing into a full FIFO. For example, consider an empty FIFO that is receiving read pulses. Because the FIFO is empty, the read pulses are ignored by the FIFO, and nothing happens. Next, a single word is written Page 11 of 17
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW. Data outputs (Q0 to Q8) are in a high impedance condition between read operations (R HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode. When one word is in the FIFO, the falling edge of R initiates a HIGH-to-LOW transition of EF. The rising edge of R causes the data outputs to go to the high impedance state and remain such until a write is performed. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read tWEF after a valid write.
Document #: 38-06001 Rev. *C
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into the FIFO, with a signal that is asynchronous to the read signal. The (internal) state machine in the FIFO goes from empty to empty+1. However, it does this asynchronously with respect to the read signal, so that the effective pulse width of the read signal cannot be determined, because the state machine does not look at the read signal until it goes to the empty+1 state.
Similarly, the minimum write pulse width may be violated by trying to write into a full FIFO, and asynchronously performing a read. The empty and full flags are used to avoid these effective pulse width violations, but to do this and operate at the maximum frequency, the flag must be valid at the beginning of the next cycle.
Figure 13. Depth Expansion
XO W FF 9 D 9
R EF 9 Q FL
CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3
VCC
XI
XO FULL 9
FF
EF
EMPTY
CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3
FL
XI
XO
*
FF 9
MR
CY7C419 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432/3
EF
FL
XI
* FIRST DEVICE
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Ordering Information
Speed (ns) 10 Ordering Code CY7C421-10AC CY7C421-10JC CY7C421-10JXC CY7C421-10PC CY7C421-10VC 15 CY7C421-15AC CY7C421-15AXC CY7C421-15JC CY7C421-15JI CY7C421-15VI 20 CY7C421-20JC CY7C421-20JXC CY7C421-20PC CY7C421-20VC CY7C421-20VXC CY7C421-20JI CY7C421-20JXI 25 CY7C421-25JC CY7C421-25PC CY7C421-25VC CY7C421-25JI CY7C421-25PI 30 CY7C421-30JC CY7C421-30PC CY7C421-30JI 40 CY7C421-40JC CY7C421-40PC CY7C421-40VC CY7C421-40JI 65 CY7C421-65JC CY7C421-65PC CY7C421-65VC CY7C421-65JI Package Type A32 J65 J65 P21 V21 A32 A32 J65 J65 V21 J65 J65 P21 V21 V21 J65 J65 J65 P21 V21 J65 P21 J65 P21 J65 J65 P21 V21 J65 J65 P21 V21 J65 Package Type 32-Pin Thin Plastic Quad Flatpack 32-Pin Plastic Leaded Chip Carrier 32-Pin Pb-Free Plastic Leaded Chip Carriers 28-Pin (300-Mil) Molded DIP 28-Pin (300-Mil) Molded SOJ 32-Pin Thin Plastic Quad Flatpack 32-Pin Pb-Free Thin Plastic Quad Flatpack 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier 28-Pin (300-Mil) Molded SOJ 32-Pin Plastic Leaded Chip Carrier 32-Pin Pb-Free Plastic Leaded Chip Carriers 28-Pin (300-Mil) Molded DIP 28-Pin (300-Mil) Molded SOJ 28-Pin (300-Mil) Pb-Free Molded SOJ 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier 28-Pin (300-Mil) Molded DIP 28-Pin (300-Mil) Molded SOJ 32-Pin Plastic Leaded Chip Carrier 28-Pin (300-Mil) Molded DIP 32-Pin Plastic Leaded Chip Carrier 28-Pin (300-Mil) Molded DIP 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier 28-Pin (300-Mil) Molded DIP 28-Pin (300-Mil) Molded SOJ 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier 28-Pin (300-Mil) Molded DIP 28-Pin (300-Mil) Molded SOJ 32-Pin Plastic Leaded Chip Carrier Industrial Industrial Commercial Industrial Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial
Document #: 38-06001 Rev. *C
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Package Diagrams
Figure 14. 32-Pin Thin Plastic Quad Flat Pack A32 (51-85063)
51-85063-*B
Figure 15. 32-Pin Plastic Leaded Chip Carrier J65 (51-85002)
51-85002-*B
Document #: 38-06001 Rev. *C
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Package Diagrams (continued)
Figure 16. 28-Pin (300-Mil) PDIP P21 (51-85014)
SEE LEAD END OPTION
14
1
DIMENSIONS IN INCHES [MM] MIN. MAX.
0.260[6.60] 0.295[7.49]
REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms
15
28
0.030[0.76] 0.080[2.03]
SEATING PLANE 1.345[34.16] 1.385[35.18]
0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30]
0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50]
3 MIN.
0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79]
0.310[7.87] 0.385[9.78] SEE LEAD END OPTION
LEAD END OPTION (LEAD #1, 14, 15 & 28)
51-85014-*D
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Package Diagrams (continued)
Figure 17. 28-Pin (300-Mil) Molded SOJ V21(51-85031)
51-85031-*C
Document #: 38-06001 Rev. *C
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Document History Page
Document Title: CY7C419, CY7C421, CY7C425, CY7C429, CY7C433, 256/512/1K/2K/4Kx9 Asynchronous FIFO Document Number: 38-06001 Rev. ** *A *B ECN No. 106462 122332 383597 Orig. of Change SZV RBI PCX Submission Date 07/11/01 12/30/02 See ECN Description of Change Change from Spec Number: 38-00079 to 38-06001 Added power up requirements to maximum ratings information. Added Pb-Free Logo Added to Part-Ordering Information: CY7C419-10JXC, CY7C419-15JXC, CY7C419-15VXC, CY7C421-10JXC, CY7C421-15AXC, CY7C421-20JXC, CY7C421-20VXC, CY7C425-10AXC, CY7C425-10JXC, CY7C425-15JXC, CY7C425-20JXC, CY7C425-20VXC, CY7C429-10AXC, CY7C429-15JXC, CY7C429-20JXC, CY7C433-10AXC, CY7C433-10JXC, CY7C433-15JXC, CY7C433-20AXC, CY7C433-20JXC Added CY7C421-20JXI Removed CY7C419/25/29/33 from the ordering information table Removed 26-Lead CerDIP, 32-Lead RLCC, 28-Lead molded DIP packages from the data sheet Removed Military Information
*C
2623658
VKN/PYRS
12/17/08
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(c) Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-06001 Rev. *C
All products and company names mentioned in this document may be the trademarks of their respective holders.
Revised December 09, 2008
Page 17 of 17
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